Field of the Invention
The invention relates to an integrated circuit (IC), and more particularly to an integrated circuit having scan test architecture and a method for establishing the scan test architecture in the integrated circuit.
Description of the Related Art
With the growing complexity of circuit designs, more transistors are being implemented on a single chip. With the growing complexity of current chip design, the test design of integrated circuit will become increasingly important. Therefore, a good test design method is needed in the chip design flow, to diagnose defects in the manufacturing process of the complex system-on-chip (SOC) integrated circuit early.
For complex integrated circuits, when the used logic units are increased, the time required for performing a scan test is increased, increasing the cost of testing the integrated circuit. Therefore, a serialized compressed scan architecture (SCSA) is used to perform a scan test in the design for testability (DFT) of the integrated circuits, wherein the SCSA can use the limited test input pins/pads and the output pins/pads to substantially increase the number of scan chains. When the number of scan chains is increased, the length of the scan chains is decreased, thereby decreasing testing time. Furthermore, by using the SCSA to compress the test data, the test data quantity can be decreased. Therefore, the test time is also decreased, thereby decreasing the test cost of the integrated circuits.